Specific Electronic Platform to Test the Influence of Hypervisors on the Performance of Embedded Systems

[EN] Some complex digital circuits must host various operating systems in a single electronic platform to make real-time and not-real-time tasks compatible or assign different priorities to current applications. For this purpose, some hardware–software techniques—called virtualization—must be integrated to run the operating systems independently, as isolated in different processors: virtual machines. These are monitored and managed by a software tool named hypervisor, which is in charge of allowing each operating system to take control of the hardware resources. Therefore, the hypervisor determines the effectiveness of the system when reacting to events. To measure, estimate or compare the performance of different ways to configure the virtualization, our research team has designed and implemented a specific testbench: an electronic system, based on a complex System on Chip with a processing system and programmable logic, to configure the hardware–software partition and show merit figures, to evaluate the performance of the different options, a field that has received insufficient attention so far. In this way, the fabric of the Field Programmable Gate Array (FPGA) can be exploited for measurements and instrumentation. The platform has been validated with two hypervisors, Xen and Jailhouse, in a multiprocessor System-on-Chip, by executing real-time operating systems and application programs in different contexts.This work has been supported by the Basque Government within the project HAZITEK ZE-2020/00022 as well as the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264 and FEDER fund

Evaluating Latency in Multiprocessing Embedded Systems for the Smart Grid

Smart grid endpoints need to use two environments within a processing system (PS), one with a Linux-type operating system (OS) using the Arm Cortex-A53 cores for management tasks, and the other with a standalone execution or a real-time OS using the Arm Cortex-R5 cores. The Xen hypervisor and the OpenAMP framework allow this, but they may introduce a delay in the system, and some messages in the smart grid need a latency lower than 3 ms. In this paper, the Linux thread latencies are characterized by the Cyclictest tool. It is shown that when Xen hypervisor is used, this scenario is not suitable for the smart grid as it does not meet the 3 ms timing constraint. Then, standalone execution as the real-time part is evaluated, measuring the delay to handle an interrupt created in programmable logic (PL). The standalone application was run in A53 and R5 cores, with Xen hypervisor and OpenAMP framework. These scenarios all met the 3 ms constraint. The main contribution of the present work is the detailed characterization of each real-time execution, in order to facilitate selecting the most suitable one for each application.This work has been supported by the Ministerio de Economía y Competitividad of Spain within the project TEC2017-84011-R and FEDER funds as well as by the Department of Education of the Basque Government within the fund for research groups of the Basque university system IT978-16. It has also been supported by the Basque Government within the project HAZITEK ZE-2020/00022 as well as the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264; in both cases, they have been financed through the Fondo Europeo de Desarrollo Regional 2014-2020 (FEDER funds). It has also been supported by the University of the Basque Country within the scholarship for training of research staff with code PIF20/135

A Fixed-Latency Architecture to Secure GOOSE and Sampled Value Messages in Substation Systems

International Electrotechnical Commission (IEC) 62351-6 standard specifies the security mechanisms to protect real-time communications based on IEC 61850. Generic Object Oriented Substation Events (GOOSE) and Sampled Value (SV) messages must be generated, transmitted and processed in less than 3 ms, which challenges the introduction of IEC 62351-6. After evaluating the security threats to IEC 61850 communications and the state of the art in GOOSE and SV security, this work presents a novel architecture based on wire-speed processing able to provide message authentication and confidentiality. This architecture has been implemented and tested to evaluate its performance, resource usage, and the latency introduced. Other proposals in the scientific literature do not support real-time traffic, so they are not suitable for GOOSE and SV messages. Whereas the others exceed the target latency of 3 ms or do not comply with the standards, our design authenticates and encrypts real-time IEC 61850 data in less than 7 mu s-predictable latency-, and complies with IEC 62351:2020.This work was supported in part by the Ministerio de Economia y Competitividad of Spain under Project TEC2017-84011-R, in part by Fondo Europeo de Desarrollo Regional (FEDER) Funds through the Doctorados Industriales program under Grant DI-15-07857, and in part by the Department of Education, Linguistic Policy and Culture of the Basque Government through the Fund for Research Groups of the Basque University System under Grant IT978-16

Encryption AXI Transaction Core for Enhanced FPGA Security

The current hot topic in cyber-security is not constrained to software layers. As attacks on electronic circuits have become more usual and dangerous, hardening digital System-on-Chips has become crucial. This article presents a novel electronic core to encrypt and decrypt data between two digital modules through an Advanced eXtensible Interface (AXI) connection. The core is compatible with AXI and is based on a Trivium stream cipher. Its implementation has been tested on a Zynq platform. The core prevents unauthorized data extraction by encrypting data on the fly. In addition, it takes up a small area—242 LUTs—and, as the core’s AXI to AXI path is fully combinational, it does not interfere with the system’s overall performance, with a maximum AXI clock frequency of 175 MHz.This work has been supported within the fund for research groups of the Basque university system IT1440-22 by the Department of Education and within the PILAR ZE-2020/00022 and COMMUTE ZE-2021/00931 projects by the Hazitek program, both of the Basque Government, the latter also by the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264 and IDI-20220543 and through the Fondo Europeo de Desarrollo Regional 2014–2020 (FEDER funds)

MACsec Layer 2 Security in HSR Rings in Substation Automation Systems

The smart-grid concept takes the communications from the enclosed and protected environment of a substation to the wider city or nationwide area. In this environment, cyber security takes a key role in order to secure the communications. The challenge is to be able to secure the grid without impacting the latency while, at the same time, maintaining compatibility with older devices and non secure services. At the lower level, added security must not interfere with the redundancy and the latency required for the real-time substation automation communications. This paper studies how to integrate IEEE MAC Security standard (MACsec) in the substation environment, especially when used in substation system communications that have stringent response time requirements and zero recovery time as defined in IEC 62439-3.This work has been supported by the Ministerio de Economia y Competitividad of Spain within the project TEC2014-53785-R, and it has been carried out inside the Research and Education Unit UFI11/16 of the UPV/EHU and partially supported by the Basque Government within the funds for research groups of the Basque University system IT978-16 and within the project TFactory ER-2014/0016. In addition, FEDER funds and UPV/EHU Ph.D. scholarship funding are acknowledged

Functional Verification for SEU Emulation in FPGA Designs

Comunciación JCRA 2014, Actas de las XIV Jornadas de Computación Reconfigurable y Aplicaciones (JCRA 2014)In this paper techniques to detect failures in a FPGA are presented and their application to SEU (Single Event Upset) emulation applications is discussed. SEU emulation in FPGAs consists on programming the device with a configuration file that has an erroneous bit, emulating the effect of a SEU. Once the device has been erroneously programmed a verification method is needed to evaluate the criticality of the modified bits. In this work two verification approaches (hardware verification and software verification) are implemented, experimental results are obtained and conclusions are taken.This work was carried out in the R&D Unit UFI11/16 of the UPV/EHU, and supported by the Ministerio de Ciencia e Innovacion of Spain within the projects TEC2011-28250-C02-01/2, and by the Basque Governments Department of Education, Universities and Research within the research fund of the Basque university system IT394-10

Fault Injection System for SEU Emulation in Zynq SoCs

Articulo Congreso DCIS 2014This paper presents a fault injection method for SEU (Single Event Upset) emulation in FPGAs based on loading at the programmable logic a configuration file with an erroneous bit. A "Xilinx Zynq®-7000 All Programmable SoC" device has been used to implement it, which combines a hard microprocessor (Processing System PS) with Programmable Logic (PL). The emulation tool is fully implemented on the Zynq chip, which means that neither additional external equipment nor PCB modifications are needed. Communications to external devices that slow down the configuration process are avoided, so a high fault-injection rate is achieved. Previous works consider including fault injection circuitry at the PL. This circuitry can be affected by a faulty configuration file, leading the device to an unrecoverable state, which is named as "injection side effects". In the method proposed in this paper the injection is implemented in the processing system of the Zynq device, making the injection system independent to the programmable logic and avoiding the previously mentioned effect. This method allows using complete bitstreams, partial bitstreams and one-frame bitstreams to inject faults. A comparison is done so as to find the most appropriate bitstream type.This work was carried out in the R&D Unit UFI11/16 of the UPV/EHU, and supported by the Ministerio de Ciencia e Innovacion of Spain within the projects TEC2011–28250-C02-01/2, by the UPV/EHU within the project US13/13 and by the Basque Governments Department of Education, Universities and Research within the research fund of the Basque university system IT394–10

Fast and efficient address search in System-on-a-Programmable-Chip using binary trees

One processing task in Ethernet nodes is to manage Media Access Control (MAC) addresses: search, insert new, and delete old ones. For this purpose, Content-Addressable Memorys (CAMs) offer low latency and no collisions; however, they consume too many electronic resources, and working frequency is constrained. On the other hand, hash tables demand few circuits allowing fast operations; unfortunately, collisions often occur, causing delays in the process. Finally, binary trees arise as one efficient technique to search addresses by hardware, although updating them is complex. The design presented in this paper, based on an Adelson-Velsky and Landis (AVL) binary tree, takes advantage of the mixed hardware/software capabilities of Multiprocessor Programmable System-on-a-Chip (MPSoC) devices. It forwards frames on the fly: a hardware core, searches addresses in an AVL tree, and a program inserts and deletes them. This solution requires few resources and, to the best of our knowledge, is the first to manage MAC addresses in an AVL tree and to exploit a hardware/software System-on-a-Chip (SoC) for this purpose